In typical dynamic random access memories (DRAMs) there is a multiplexed address. The row address is received first. The row address selects a word line to be enabled. Each memory cell along the enabled word line couple data to a bit line to which it is coupled. A sense amplifier detects the data and amplifies it on the bit line and in so doing refreshes the data in the enabled cell. An access thus begins with a row address. There are buffers which receive this address. These address buffers, although necessary for reliable operation of the DRAM, cause a delay. Additionally these address buffers are clocked by a signal which is derived from an externally provided signal, *RAS. In a conventional input buffer of the prior art, the initial stage, after the input protection, was a two-input NAND gate. One input was for the clock signal and the other was for the address signal. Other buffering circuits comprised primarily of inverters followed this initial stage. The worst case delay was for the case in which both the address and this clock signal simultaneously switched from a logic low to a logic high. In a NAND gate there are two N channel transistors in series with each other which become conductive for this case. These two N channel transistors in series becoming simultaneously conductive was slower than any of the other combinations of transitions. With two signals having two possible states, there are four possible conditions. To compensate for this one weakest condition, a technique was developed to precharge a node in the input chain to the logic state which results from both inputs being a logic high. Consequently, the input buffer would thus already be in the condition which would otherwise be the slowest condition to reach.
Another characteristic of DRAMs is that the memory cells must all be periodically refreshed. A typical refresh requirement for a DRAM cell for reliable operation is once every 4 milliseconds (ms). Consequently, every memory cell must be refreshed every 4 ms. This is achieved by enabling all of the word lines at least once every 4 ms. One way this can be achieved is by requiring the user of the DRAM to ensure that all of the word lines are enabled at least once every 4 ms. Another approach that is well known is to include an on-board counter for refresh purposes. The DRAM would then run either a data cycle or a refresh cycle. A data cycle was one in which data was either input to or output from the DRAM. A refresh cycle was a cycle for refreshing the memory cells along a word line or word lines corresponding to a single row address. The on-board counter was used for generating the proper row addresses for selecting the word lines for refreshing purposes. Because internal refresh was used in conjunction with the row address, there tended to be extra delay in the address buffer. The addresses generated from the refresh counter circuitry interfered with the normal address buffer input path. There were also timing differentials which caused problems in design and layout in order to match various delays.